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High Voltage Latch-Up Proof, Dual SPDT Switches ADG5436
FEATURES
Latch-up proof 8 kV HBM ESD rating Low on resistance (<10 ) 9 V to 22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at 15 V, 20 V, +12 V, and +36 V VSS to VDD analog signal range
FUNCTIONAL BLOCK DIAGRAMS
ADG5436
S1A D1 S1B IN1 IN2 S2A D2 S2B
APPLICATIONS
Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1. TSSOP Package
ADG5436
S1A D1 S1B S2A D2 S2B
LOGIC
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2. LFCSP Package
GENERAL DESCRIPTION
The ADG5436 is a monolithic CMOS device containing two independently selectable single-pole/single-throw (SPDT) switches. An EN input on the LFCSP package enables or disables the device. When disabled, all channels switch off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. 2. Low RON. 3. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5436 can be operated from dual supplies up to 22 V. 4. Single-supply operation. For applications where the analog signal is unipolar, the ADG5436 can be operated from a single-rail power supply up to 40 V. 5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. 6. No VL logic power supply required.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
09204-002
IN1
IN2
EN
09204-001
ADG5436 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 20 V Dual Supply ....................................................................... 4 12 V Single Supply ........................................................................ 5 36 V Single Supply ........................................................................ 6 Continuous Current per Channel, Sx or Dx ............................. 7 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Truth Table For Switches ..............................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits ..................................................................................... 14 Terminology .................................................................................... 16 Trench Isolation .............................................................................. 17 Applications Information .............................................................. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5436 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON tOFF Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) 2.0 0.8 0.002 0.1 5 170 235 173 230 124 160 55 200 -78 -58 0.009 102 -0.7 18 62 83 V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ 25C -40C to +85C -40C to +125C VDD to VSS 9.8 11 0.35 0.7 1.2 1.6
0.05 0.25 0.1 0.4 0.1 0.4
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max
Test Conditions/Comments
14
16
VS = 10 V, IS = -10 mA; see Figure 25 VDD = +13.5 V, VSS = -13.5 V VS = 10 V , IS = -10 mA
0.9 2
1.1 2.2
VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = m10 V; see Figure 28 VS = 10 V, VD = m10 V; see Figure 28 VS = VD = 10 V; see Figure 24
0.75 2 2
3.5 12 12
VIN = VGND or VDD
285 280 193
316 351 218 18
RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 32 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 1 k, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 30 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz
Rev. 0 | Page 3 of 20
ADG5436
Parameter POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C
45 55 0.001
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max V min/V max
Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
70 1
9/22
Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = -20 V 10%, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON tOFF Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth 25C -40C to +85C -40C to +125C VDD to VSS
9 10 0.35 0.7 1.5 1.8 0.05 0.25 0.1 0.4 0.1 0.4 13 15
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ
Test Conditions/Comments
VS = 15 V, IS = -10 mA; see Figure 25 VDD = +18 V, VSS = -18 V VS = 15 V , IS = -10 mA
0.9 2.2
1.1 2.5
VS = 15 V, IS = -10 mA VDD = +22 V, VSS = -22 V VS = 15 V, VD = m 15 V; see Figure 28 VS = 15 V, VD = m 15 V; see Figure 28 VS = VD = 15 V; see Figure 24
0.75 2 2
3.5 12 12
2.0 0.8 0.002 0.1 5 158 217 164 213 110 152 50 250 -78 -58 0.007 100
Rev. 0 | Page 4 of 20
VIN = VGND or VDD
260 256 173
293 287 194 15
RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 32 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 1 k, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 30
ADG5436
Parameter Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C -0.6 18 63 82
50 70 0.001
-40C to +85C
-40C to +125C
Unit dB typ pF typ pF typ pF typ A typ A max A typ V min/V max
Test Conditions/Comments RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = -22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
110
9/22
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD
19 22 0.4 0.8 4.4 5.5 0.05 0.25 0.1 0.4 0.1 0.4 0.75 3.5 27 31
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ
Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 10 V, IS = -10 mA; see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA
1 6.5
1.2 7.5
VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28 VS = VD = 1 V/10 V; see Figure 24
Drain Off Leakage, ID (Off )
2 2
12 12
Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON tOFF Break-Before-Make Time Delay, tD Charge Injection, QINJ
2.0 0.8 0.002 0.1 5 250 346 250 358 135 178 125 80
Rev. 0 | Page 5 of 20
VIN = VGND or VDD
437 445 212
501 512 237 50
RL = 300 , CL = 35 pF VS = 8 V; see Figure 31 RL = 300 , CL = 35 pF VS = 8 V; see Figure 33 RL = 300 , CL = 35 pF VS = 8 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 32 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 34
ADG5436
Parameter Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD VDD
1
25C -78 -58 0.075 106 -1.3 22 67 85
40 50
-40C to +85C
-40C to +125C
Unit dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/V max
Test Conditions/Comments RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 1 k, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 30 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
65
9/40
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD
10.6 12 0.35 0.7 2.7 3.2 0.05 0.25 0.1 0.4 0.1 0.4 0.75 3.5 15 17
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max
Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 30 V, IS = -10 mA; see Figure 25 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = -10 mA
0.9 3.8
1.1 4.5
VS = 0 V to 30 V, IS = -10 mA VDD =39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 28 VS = 1 V/30 V, VD = 30 V/1 V; see Figure 28 VS = VD = 1 V/30 V; see Figure 24
Drain Off Leakage, ID (Off )
2 2
12 12
Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON
2.0 0.8 0.002 0.1 5 174 246 180 247
VIN = VGND or VDD
270 270
303 301
Rev. 0 | Page 6 of 20
RL = 300 , CL = 35 pF VS = 18 V; see Figure 31 RL = 300 , CL = 35 pF VS = 18 V; see Figure 33
ADG5436
Parameter tOFF Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD VDD
1
25C 127 179 55 250 -78 -58 0.03 98 -0.8 19 40 78
80 100
-40C to +85C 193
-40C to +125C 215 18
Unit ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/V max
Test Conditions/Comments RL = 300 , CL = 35 pF VS = 18 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 18 V; see Figure 32 VS = 18 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 1 k, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 30 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
130
9/40
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = -15 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = +20 V, VSS = -20 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 36 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
122 217 130 229 84 150 110 196
77 116 80 121 56 90 70 109
44 53 45 54 36 48 42 52
mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum
Rev. 0 | Page 7 of 20
ADG5436 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, JA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP Reflow Soldering Peak Temperature, Pb Free
1
Rating 48 V -0.3 V to +48 V +0.3 V to -48 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 375 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 112C/W 30.4C/W 260(+0/-5)C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 See Table 5.
Rev. 0 | Page 8 of 20
ADG5436 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 S1A 15 IN1
IN1 1 S1A 2 D1 3 S1B 4
16 15 14
NC NC NC
VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B
13 11 10 9
ADG5436
D1 1 S1B 2 VSS 3 GND 4
09204-003
PIN 1 INDICATOR
13 NC
14 NC
12 EN 11 VDD 10 S2B 9 D2
ADG5436
TOP VIEW (Not to Scale)
GND 6 NC 7 NC 8
D2 S2A
NC = NO CONNECT
S2A 8
IN2 6
NC 7
NC 5
IN2
NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT.
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 1 4 2 5 3 6 4 7, 8, 14 to 16 5, 7, 13, 14 9 6 10 8 11 9 12 10 13 11 N/A 12 EP Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD EN Exposed Pad Function Logic Control Input 1. Source Terminal 1A. This pin can be an input or output. Drain Terminal 1. This pin can be an input or output. Source Terminal 1B. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. Logic Control Input 2. Source Terminal 2A. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Source Terminal 2B. This pin can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, INx logic inputs determine the on switches. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE FOR SWITCHES
Table 8. ADG5436 TSSOP Truth Table
INx 0 1 SxA Off On SxB On Off
Table 9. ADG5436 LFCSP Truth Table
EN 0 1 1 INx X 0 1 SxA Off Off On SxB Off On Off
Rev. 0 | Page 9 of 20
09204-004
ADG5436 TYPICAL PERFORMANCE CHARACTERISTICS
16 TA = 25C 14 12 ON RESISTANCE ()
10
12
VDD = +10V VDD = +9V VSS = -10V VSS = -9V VDD = +11V VSS = -11V
TA = 25C 10 VDD = 32.4V VSS = 0V
ON RESISTANCE ()
VDD = 36V VSS = 0V 8
8 6 4 VDD10 +13.5V = VSS = -13.5V VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V
6
VDD = 39.6V VSS = 0V
4
2
2 0 -20
0
09204-134
-15
-10
-5
0
5
10
15
20
0
5
10
15
20
25
30
35
40
45
VS, VD (V)
VS, VD (V)
Figure 5. On Resistance vs. VS, VD (Dual Supply)
12
VDD = +18V VSS = -18V
Figure 8. On Resistance vs. VS, VD (Single Supply)
18 16 14
10
ON RESISTANCE ()
ON RESISTANCE ()
8
VDD = +20V VSS = -20V VDD = +22V VSS = -22V
12 10 8 6 4
TA = +125C TA = +85C TA = +25C TA = -40C
6
4
2 2 0 -25
TA = 25C
09204-135
-20
-15
-10
-5
0 VS, VD (V)
5
10
15
20
25
-5
0 VS, VD (V)
5
10
15
Figure 6. On Resistance vs. VS, VD (Dual Supply) Included
25
TA = 25C VDD = +10V VSS = 0V VDD = 10.8V VSS = 0V
Figure 9. On Resistance vs. VD or VS for Different Temperatures, 15 V Dual Supply
16 14 12
ON RESISTANCE ()
20
ON RESISTANCE ()
VDD = +9V VSS = 0V
TA = +125C
15
VDD = 11V VSS = 0V VDD = 13.2V VSS = 0V
10 8 6 4
TA = +85C TA = +25C TA = -40C
10
VDD = 12V VSS = 0V
5 2 0
VDD = +20V VSS = -20V 0 -20 -15 -10
0
2
4
6
8 VS, VD (V)
10
12
14
09204-041
-5
0 VS, VD (V)
5
10
15
20
Figure 7. On Resistance vs. VS, VD (Single Supply)
Figure 10. On Resistance vs. VD or VS for Different Temperatures, 20 V Dual Supply
Rev. 0 | Page 10 of 20
09204-141
09204-140
VDD = +15V VSS = -15V 0 -15 -10
09204-042
ADG5436
30 VDD = 12V VSS = 0V
0.8 0.6
LEAKAGE CURRENT (nA)
25 ON RESISTANCE () TA = +125C 20 TA = +85C 15 TA = +25C TA = -40C
VDD = +20V VSS = -20V VBIAS = +15V/-15V
ID, IS (ON) + + ID (OFF) - + IS (OFF) + -
0.4 0.2 0
10
-0.2 -0.4
ID, IS (ON) - - IS (OFF) - + ID (OFF) + -
5
09204-142
0
2
4
6 VS, VD (V)
8
10
12
0
25
50
75
100
125
TEMPERATURE (C)
Figure 11. On Resistance vs. VD or VS for Different Temperatures, 12 V Single Supply
16 14 TA = +125C TA = +85C TA = +25C TA = -40C
LEAKAGE CURRENT (nA)
Figure 14. Leakage Currents vs. Temperature, 20 V Single Supply
0.6 VDD = 12V VSS = 0V VBIAS = 1V/10V 0.4 ID, IS (ON) + +
12
ON RESISTANCE ()
10 8 6 4 2 0
0.2 IS (OFF) + - 0 ID, IS (ON) - - -0.2
ID (OFF) - +
VDD = 36V VSS = 0V
09204-143
ID (OFF) + -
50
IS (OFF) - +
09204-046
0
5
10
15
20 VS, VD (V)
25
30
35
40
0
25
75
100
125
TEMPERATURE (C)
Figure 12. On Resistance vs. VS (VD) for Different Temperatures, 36 V Single Supply
0.6
Figure 15. Leakage Currents vs. Temperature, 12 V Single Supply
0.8
VDD = +15V VSS = -15V VBIAS = +10V/-10V
ID, IS (ON) + + 0.6 LEAKAGE CURRENT (nA) ID (OFF) - + 0.4
VDD = 36V VSS = 0V VBIAS = 1V/30V
ID, IS (ON) + +
0.4
LEAKAGE CURRENT (nA)
0.2
IS (OFF) + -
ID (OFF) - + IS (OFF) + -
0.2 0 -0.2 ID, IS (ON) - - -0.4 -0.6 IS (OFF) - + ID (OFF) + -
0
-0.2
ID, IS (ON) - - ID (OFF) + - IS (OFF) - +
-0.4
09204-047
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 16. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
09204-049
-0.6
09204-048
0
-0.6
ADG5436
TA = 25C -10 VDD = +15V VSS = -15V -20
OFF ISOLATION (dB)
0
0 -10 -20 -30
TA = 25C VDD = +15V VSS = -15V
-30
ACPSRR (dB)
-40 -50 -60 -70 -80 -90
09204-044
-40 -50 -60 -70 -80 -90
NO DECOUPLING CAPACITORS
DECOUPLING CAPACITORS
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Off Isolation vs. Frequency
0 -10 -20
CROSSTALK (dB)
Figure 20. ACPSRR vs. Frequency
0.10 0.09 0.08 0.07
THD + N (%)
TA = 25C VDD = +15V VSS = -15V
LOAD = 1k TA = 25C VDD = 12V, VSS = 0V, VS = 6V p-p
-30 -40 -50 -60 -70 -80 -90
09204-040
0.06 0.05 0.04 VDD = 36V, VSS = 0V, VS = 18V p-p 0.03 0.02 VDD = 15V, VSS = 15V, VS = 15V p-p 0.01
100k
1M
10M
100M
1G
0
5k
10k FREQUENCY (Hz)
15k
20k
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
450
Figure 21. THD + N vs. Frequency
0
TA = 25C
400 350 INSERTION LOSS (dB) 300 250 200 150 100 50 0 -20
-0.5 -1.0
VDD = +20V VSS = -20V VDD = +36V VSS = 0V
TA = 25C VDD = +15V VSS = -15V
CHARGE INJECTION (pC)
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0
VDD = +15V VSS = -15V
VDD = +12V VSS = 0V
09204-034
-4.5
20 30 40
-10
0
10 VS (V)
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 19. Charge Injection vs. Source Voltage
Figure 22. Bandwidth
Rev. 0 | Page 12 of 20
09204-037
-5.0 1k
09204-039
-100 10k
0
VDD = 20V, VSS = 20V, VS = 20V p-p
09204-038
-100 1k
-100 1k
ADG5436
400 350 300 250
TIME (ns)
VDD = 12V VSS = 0V VDD = 36V VSS = 0V VDD = +20V VSS = -20V VDD = +15V VSS = -15V
200 150 100 50 0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 23. tTRANSITION Time vs. Temperature
09204-035
Rev. 0 | Page 13 of 20
ADG5436 TEST CIRCUITS
ID (ON) NC SxA/SxB Dx A
09204-025
IS (OFF) A VS SxA/SxB Dx
ID (OFF) A VD
09204-024
NC = NO CONNECT
VD
Figure 24. On Leakage
VDD 0.1F VSS
Figure 28. Off Leakage
0.1F AUDIO PRECISION VDD VSS RS
SxA/SxB
V
INx
Dx
SxA/SxB
Dx VIN RL 1k VOUT
VS V p-p
Figure 25. On Resistance
VDD 0.1F VSS 0.1F
VDD 0.1F VSS
Figure 29. THD + Noise
0.1F NETWORK ANALYZER NC 50 VS 50
NETWORK ANALYZER VOUT RL 50
VDD SxA
VSS
VDD SxA VSS SxB
SxB INx VS GND
Dx
RL 50
INx
Dx
VIN GND RL 50 VOUT
09204-032
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 26. Channel-to-Channel Crosstalk
Figure 30. Bandwidth
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50 VS 50
VDD SxA
VSS SxB
INx
Dx
VIN GND RL 50 VOUT
OFF ISOLATION = 20 log
VOUT VS
Figure 27. Off Isolation
09204-030
Rev. 0 | Page 14 of 20
09204-031
VOUT VS
09204-033
VS
09204-023
IDS
GND
ADG5436
0.1F VDD VSS 0.1F VIN 50% 50%
VDD VS SxB SxA INx VIN GND
VSS Dx RL 300 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tON
tOFF
Figure 31. Switching Times
0.1F
VDD
VSS
0.1F VIN
VDD VS SxB SxA INx VIN GND
VSS Dx RL 300 CL 35pF VOUT
VOUT
80%
tD
tD
09204-027
Figure 32. Break-Before-Make Time Delay tD
VDD 3V ENABLE DRIVE (VIN) 0V 50% 50%
VSS
VDD INx
VSS SxA SxB VS
tON (EN)
0.9VOUT OUTPUT
tOFF (EN)
0.9VOUT VIN 50 EN GND Dx
OUTPUT 35pF
09204-028
Figure 33. Enable Delay, tON (EN), tOFF (EN)
0.1F
VDD
VSS
0.1F VIN (NORMALLY CLOSED SWITCH) ON NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT OFF
VDD VS Dx
VSS SxB SxA
INx VIN GND
Figure 34. Charge Injection
Rev. 0 | Page 15 of 20
09204-029
QINJ = CL x VOUT
09204-026
300
ADG5436 TERMINOLOGY
IDD IDD represents the positive supply current. ISS ISS represents the negative supply current. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. RON RON represents the difference between the RON of any two channels. RFLAT (ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN is the digital input capacitance. tON tON represents the delay between applying the digital control input and the output switching on. tOFF tOFF represents the delay between applying the digital control input and the output switching off. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.
Rev. 0 | Page 16 of 20
ADG5436 TRENCH ISOLATION
In the ADG5436, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch.
P-WELL N-WELL
NMOS PMOS
TRENCH
BURIED OXIDE LAYER HANDLE WAFER
09204-045
Figure 35. Trench Isolation
Rev. 0 | Page 17 of 20
ADG5436 APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace and other harsh environments that are prone to latchup, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5436 high voltage switches allow single-supply operation from 9 V to 40 V and dual supply operation from 9 V to 22 V. The ADG5436 (as well as other select devices within this family) achieves an 8 kV human body model ESD rating, which provides a robust solution eliminating the need for separate protect circuitry designs in some applications.
Rev. 0 | Page 18 of 20
ADG5436 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
PIN 1 INDICATOR
4.10 4.00 SQ 3.90 0.65 BSC
0.35 0.30 0.25
13 12 EXPOSED PAD 1 16
PIN 1 INDICATOR
4 9 8 5
2.70 2.60 SQ 2.50
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADG5436BRUZ ADG5436BRUZ-REEL7 ADG5436BCPZ-REEL7
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
012909-B
Package Option RU-16 RU-16 CP-16-17
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADG5436 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09204-0-7/10(0)
Rev. 0 | Page 20 of 20

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